PATENT: SUS-LOC

The “Supplementary Symmetrical Logic Structure” referred to as (SUS-LOC) can be used to realize any “r-valued” logic function. The structure never allows a DC path between a power supply and ground, resulting in a nominally zero DC power. This low-power characteristic is useful in the realization of very-large-scale-integrated (VLSI) multiple-valued logic (MVL) circuits.

The principal features of SUS-LOC include a design structure that allows zero nominal DC power dissipation by providing no DC path between logic-level-defining power sources and ground. In the design of a logical function of radix ‘r’, the resulting structure uses ‘r-1’ power supplies to define the ‘r-1’ non-zero logic levels.

The output node of the r-valued logic function is connected with pass transistor networks to the ‘r-1’ power sources and ground. For any one combination of inputs, only one path from a power supply or ground to the output node is activated. The procedures for designing the pass-transistor networks include the choice of enhancement- or depletion-mode, NMOS or PMOS transistors, and the specification of the selected transistors’ threshold voltages.