Encryption


Encryption co-processor designed for smartcard applications.

  Fine-grain pipelined asynchronous architecture.


  First revision is based on a power-balanced binary cell library.


  Follows the NIST AES encryption standard:


  128, 192, or 256-bit key length.


  Electronic Code Book mode of operation.


  Fully-synthesized design.



Design kit based on:

     TSMC 180nm process design rules and models.


     Cadence tool set used for layout and place-and-route.